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MAX8834Y/MAX8834Z
Adaptive Step-Up Converters
with 1.5A Flash Driver
SCL
SDA
START
CONDITION
(S)
DATA LINE STABLE
DATA VALID
DATA ALLOWED TO
CHANGE
STOP
CONDITION
(P)
Figure 16. Bit Transfer
MAX8834Z and generates SCL to synchronize the data
transfer (Figure 15).
I 2 C is an open-drain bus. Both SDA and SCL are bidi-
rectional lines, connected to a positive supply voltage
through a pullup resistor. They both have Schmitt trig-
gers and filter circuits to suppress noise spikes on the
bus to assure proper device operation.
A bus master initiates communication with the
MAX8834Y/MAX8834Z as a slave device by issuing a
START (S) condition followed by the MAX8834Y/
MAX8834Z address. The MAX8834Y/MAX8834Z
address byte consists of 7 address bits and a read/
write bit (R/ W ). After receiving the proper address, the
MAX8834Y/MAX8834Z issue an acknowledge bit by
pulling SDA low during the ninth clock cycle.
Slave Address
The MAX8834Y/MAX8834Z act as a slave transmitter/
receiver. Its slave address is 0x94 for write operations
and 0x95 for read operations.
Bit Transfer
Each data bit, from the most significant bit to the least
significant bit, is transferred one by one during each
clock cycle. During data transfer, the SDA signal is
allowed to change only during the low period of the
SCL clock and it must remain stable during the high
period of the SCL clock (Figure 16).
20
START and STOP Conditions
Both SCL and SDA remain high when the bus is not
busy. The master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the MAX8834Y/
MAX8834Z, it issues a STOP (P) condition by transition-
ing SDA from low to high while SCL is high. The bus is
then free for another transmission (Figure 17). Both
START and STOP conditions are generated by the bus
master.
Acknowledge
The acknowledge bit is used by the recipient to hand-
shake the receipt of each byte of data (Figure 18). After
data transfer, the master generates the acknowledge
clock pulse and the recipient pulls down the SDA line
during this acknowledge clock pulse so the SDA line
stays low during the high duration of the clock pulse.
When the master transmits the data to the
MAX8834Y/MAX8834Z, it releases the SDA line and the
MAX8834Y/MAX8834Z take control of the SDA line and
generate the acknowledge bit. When SDA remains high
during this 9th clock pulse, this is defined as the not
acknowledge signal. The master can then generate
either a STOP condition to abort the transfer, or a
repeated START condition to start a new transfer.
Maxim Integrated
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